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I have a question after looking at this stackoverflow question (Loading and storing bytes in MIPS).

How does MIPs processor store a byte in the memory? Since the memory is word addressed. As in the question (Loading and storing bytes in MIPS) it can be seen that when we store a byte e.g, we have the following data at the following memory address locations

byte:  4   5   6   7
      FF  FF  FF  FF

When we do store byte at memory location 6 and the data stored is 90, we get the following memory state after the store byte is executed.

byte:  4   5   6   7
      FF  FF  90  FF

My question is how exactly does store byte work then?

From this example I infer that for store byte, first the processor loads the word from the required address and then replaces the byte to be stored and then stores the whole word at the memory address it was loaded from.

Is that correct?

(Update)

I think the byte enable lines or also known as the strobe lines in buses enable the processor to write a single byte instead of the whole word. So I don't think the processor needs to load the whole word first to do a store byte. If that makes sense.

AZ123
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    MIPS has byte-addressable memory, so this question is at least partially based on a misconception. – harold Jan 20 '22 at 00:11
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    What makes you think MIPS has word addressable memory? There's nothing in that question that suggests this. You can see the addresses in the address column next to the memory going up by 4 bytes per row (0,4,8,12,16,20,24). As it shows, words, equivalent to 4 bytes of storage, takes 4 different addresses, which is the definition of byte addressable. – Erik Eidt Jan 20 '22 at 00:25
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    If MIPS has word-addressable memory, by definition it wouldn't have `sb`. Semi-related: [Can modern x86 hardware not store a single byte to memory?](https://stackoverflow.com/a/46818162) discusses DEC Alpha which is byte-addressable but doesn't have a byte-store. And how the L1d cache on many non-x86 CPUs takes extra time to commit a byte store, vs. a full word or pair of words, like an internal atomic RMW to update the ECC bits. – Peter Cordes Jan 20 '22 at 00:37
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    Maybe you're mixing up word-addressable with word-modifiable? In that case yeah, the followup to the question I linked is actually extremely relevant: [Are there any modern CPUs where a cached byte store is actually slower than a word store?](https://stackoverflow.com/q/54217528) has examples of ARM and PowerPC doing RMW cycles to commit to L1d cache. Without cache, most CPUs have byte-enable lines on external data busses, though, if there isn't ECC to update. e.g. [How many and what size cycles will be needed to perform longword transferred to the CPU](https://stackoverflow.com/q/49882244) – Peter Cordes Jan 20 '22 at 01:43
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    The idea of implementing `sb` as load-modify-store in hardware is not so silly: I was already thinking about such an implementation for an FPGA-based CPU... – Martin Rosenau Jan 20 '22 at 12:32
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    MIPS is an instruction set architecture (as is RISCV) -- there's a difference between an ISA and an its implementations. An ISA doesn't have to specify how something works internally, they usually just state the program-observable effect of the various instructions, then an implementation is free to use any approach that meets these effects. Caches on these processors tend to hide byte-sized operations in favor of line-sized interactions with cacheable main memory. – Erik Eidt Jan 20 '22 at 20:27

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