Rising Edge Led Counter Problems in VHDL

Question

I'm new to fpga and VHDL in general (I'm using a fpga aprox. 2 weeks now). I am trying to create a project that lights up LEDs in order. First of all I made a falling edge detector for the button. And then I created a std_logic_vector for LEDs. But I can't detect a signal change in fallen edge detection. Because of that I can't change LED state. There is my testbench for simulation. I don't have any idea what's going on. Thanks for your answers and sorry for my bad English.

Code:

library ieee;
use ieee.std_logic_1164.all;

entity sequential_led is
end sequential_led;

architecture seq_led of sequential_led is
    signal clk : std_logic := '0';
    --signal rst : std_logic := '1';
    --signal rstb : std_logic := '1';
    signal i : natural := 0;
    signal dus_next : std_logic := '0';
    signal dusen : std_logic := '0';    
    signal button : std_logic := '0';
    signal led : std_logic_vector(7 downto 0);
begin
    clk <= not clk after 1 ns;
    button <= not button after 2 ns;
    falling: 
    process begin
    if rising_edge(clk) then
        dus_next <= button;
    end if;
    wait for 100 ns;
    end process falling;
    dusen <= (not button) and dus_next;
    
    led_changes:
    process begin
    if dusen = '1' then
        i <= i + 1;
        if i = 7 then
            i <= 0;
        end if;
    end if;
    led(7-i) <= '0';
    led(i) <= '1';
    wait for 100 ns;
    end process led_changes;
    
end architecture;

Hi Ibrahim, do you have a separate piece of code for the LED control entity? It looks like you have what looks like an LED control process in `led_changes` coded directly into the test bench. If you do, it would help to see the entity you intend to control with the test bench. If not, you'll need to create one and instantiate it within the test bench. I would also take a look at [sensitivity lists](https://stackoverflow.com/questions/8991223/when-must-a-signal-be-inserted-into-the-sensitivity-list-of-a-process) and make sure your LED control process is acting as you intend. — DomasAquinas, Feb 24 '22 at 01:31
Please provide enough code so others can better understand or reproduce the problem. — Community, Feb 24 '22 at 07:39
Hi @DomasAquinas! Thank you for your help. I've successfuly fixed my code. You can view the answer if you want. Have a nice day/night! — İbrahim Varola, Feb 24 '22 at 17:55

score 0 · Accepted Answer · answered Feb 24 '22 at 17:54

UPDATE: First of all very big thanks to DomasAquinas and Martin Thompson! After 3 days of work, I finally finished my little LED project.

Change: I've made sure all of processes has a sensivity trigger.

For falling process I've included 'clk' signal for sensivity.

For led_change process I've included 'dusen' signal for sensivity.

Code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity sequential_led is
    port(
        clk     : in std_logic;
        button  : in std_logic;
        led     : out std_logic_vector(7 downto 0) := (others => '0') 
    );
    signal dus_next : std_logic;
    signal i        : natural range 0 to 7;
    signal dusen    : std_logic := '0';

end sequential_led;

architecture seq_led of sequential_led is
begin
    falling: 
    process(clk) begin
    if rising_edge(clk) then
        dus_next <= button;
    end if;
    end process falling;
    dusen <= (not button) and dus_next;
    
    led_changes:
    process(dusen) begin
    if dusen = '1' then
        i <= i + 1;
        if i = 7 then
            i <= 0;
        end if;
        led(i) <= '1';
        led(i+7) <= '0';

    end if;
    end process led_changes;
    
end architecture;

Rising Edge Led Counter Problems in VHDL

1 Answers1