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While searching for solutions related to the Verilog code error message 'range must be bounded by constant expressions", I came across answers that pointed to the SystemVerilog LRM's use of part-select addressing such as this earlier post.

I successfully applied such descriptions for most of my vector assignments.

There was, however, a description that the tool didn't like. I searched for an alternative and found that the expression [ lsb_base_expr +- width_expr ] could work. I tried it and it seems to be working. I want to find where the LRM describes it or if it is somehow something I should not use for synthesis purposes.

nanoeng
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2 Answers2

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Sections 7.4.6 Indexing and slicing of arrays and 11.5.1 Vector bit-select and part-select addressing both describe this syntax.

This gets synthesized as a barrel shifter. The fact that you cannot have variable width operands is a language restriction, unrelated to synthesis.

dave_59
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  • Thanks a lot for the reply! Please, forgive my naive question. I tried synthesizing the RTL description for a reduced model and it does give me a barrel shifter. However, I haven't been able to visualize how that specific description can be attained from the SV's LRM. Would you mind pointing me to the way one can reach such conclusion? – nanoeng Sep 15 '22 at 15:14
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    It might help to first think of how a single bit index gets implemented. It's a giant multiplexor tree the size of the bus using the index as mux selects. Write that out as one single Boolean equation. Then write out the Boolean equation for the second bit of a 2-bit select. It gets tedious very quickly. But that is eactly what the synthesis tool is doing. As part of its optimization process, it results in what looks like to you as a barrel shifter. – dave_59 Sep 16 '22 at 05:56
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11.5.1 Vector bit-select and part-select addressing

An indexed part-select is given with the following syntax:

logic [15:0] down_vect;
logic [0:15] up_vect;
down_vect[lsb_base_expr +: width_expr]
up_vect[msb_base_expr +: width_expr]
down_vect[msb_base_expr -: width_expr]
up_vect[lsb_base_expr -: width_expr]

The msb_base_expr and lsb_base_expr shall be integer expressions, and the width_expr shall be a positive constant integer expression. Each of these expressions shall be evaluated in a self-determined context. The lsb_base_expr and msb_base_expr can vary at run time.

Serge
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