How to convert 1D data into 2D data?

Question

I have a data of 1024 bit stored in A register.

reg [1023:0] A;
reg [7:0] B [0:127]

Now I want to convert it into 2 dimensional register B. How's it possible with minimum coding in Verilog?

Answer 1

One way is to use a for loop:

module tb;

reg [1023:0] A;
reg [7:0] B [0:127];

always_comb begin
    for (int i=0; i<128; i++) begin
        B[i] = A[8*i +: 8];
    end
end

endmodule

See also +:

Answer 2

In System Verilog a streaming operator could be used for this:

module top;
  reg [1023:0] A;
  reg [7:0] B [0:127];
  always_comb begin
    B = {>>{A}};
    // this also works:
    //     {>>{B}} = A;
  end
  
  // testing
  initial begin
    for(int i = 0; i < 128; i++)
      A[i*8 +: 8] = i;
    
   #1 $finish;
  end
  always @* begin
    $display("A: %3d %3d %3d", A[7:0], A[15:8], A[1023:1016]);
    $display("B: %3d %3d %3d", B[127], B[126], B[0]);
  end
endmodule

Just note, due to the B[0:127] declaration, index [0] is the most significant one and maps to A[1023:1016]. If you want an opposite mapping, declare B[127:0].