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Questions tagged [arm-mpu]

Questions related to the ARM "memory protection unit", commonly found on [cortex-m] and other ARM CPUs.

21 questions
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Hard fault RP2040 pico Zephyr

I'm using RP2040 under Zephyr and MCUboot. The final goal is to be able to update the firmware using MCUMGR over an UART bus. MCUboot use A/B seamless (dual slot memory) method to provide a safe update algorithm. When device reboot, MCUboot check if…
Thisora
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NULL pointer protection with ARM Cortex-M MPU

The MPU in ARM Cortex-M (M0+/M3/M4/M7/etc.) is often advertised as allowing to set up protection against dereferencing the NULL pointer. But how to do this in practice? (Some online discussions, like in the Zephyr Project, indicate that the issue is…
Miro Samek
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TXM_MODULE_MANAGER_16_MPU for STMEZH7

According to the application note AN4838 page 12, STMEZH7 has only 8 regions. However, there is the following statement in the project description of STM32H747I: The TXM_MODULE_MANAGER_16_MPU is a Preprocessor define that should be added in both C…
Hamdim
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STM32H7 MPU shareable memory attribute and strongly ordered memory type

I am confused by some of the attributes of the STM32H7 MPU. I've read several documents: STM32H7 reference and programming manual, STMicro application note on MPM, etc... I've understood that shareable is exactly equivalent to non-cacheable (at…
Guillaume Petitjean
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How do I configure MPU registers in cortex m4?

I want to add a protection to a region of a memory, starting from 0x20000000. The size of the region is 64 bytes. Permission is read only, no flag set except xn. Here's how I think it should be, #define MPU_CTRL (*((volatile unsigned long*)…
Muzahir Hussain
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How to generate memory management fault in cortex m3 based microcontroller

I'm an engineering student and currently studying cortex m3 processor and it's exception handling model. I have generated and tested usage fault, bus fault, hard fault with their corresponding fault handlers. But I don't know how to generate memory…
Kalidas Tate
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ARMv6-M memory protection unit

While reading the documentation of ARMv6-M, I met for the first time the memory protection unit (which is not that complicated). According to the documentation, there is a register named the MPU_RASR (which stands for "MPU Region Attribute and Size…
TJR
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Understanding the programming of Mpu in ARM [ M3 ]

I am trying to understand how it exactly works with the alias registers of the Mpu. So here are my understandings: A. For each region there are separate RBAR and RASR registers. So, for 8 regions there are total 16 of those registers physically in…
Uchia Itachi
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MPU and Cache Relation -cortex-r4

While configuring MPU in cortex-r4 or configuring the cache, What are the memory attributes needs to considered,? What are the relation between Memory protection unit attributes with cache and memory attributes?
user3054502
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MPU Disable and Enable sequence after reset

Once the system is up and the MPU is configured and unable, after the processor reset how to enable the MPU? What are the steps need to be consider for Enabling again the MPU?
user3054502
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Is it possible to disable completely the MMU/MPU and read/write in completely arbitrary memory regions?

I recently fought with profiling the power consumption of an ARM Cortex-M4, and I wondered if it was possible to read or write in arbitrary regions of memory. What I mean is that I know that in a normal system there are layers of translation and…
Alessandro Bertulli
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Process stacks and interrupts on Cortex-M ARM cores

According to ARMv7-M and ARMv8-M reference manuals, exception stack frame is formed on currently active stack (MSP or PSP, depending on what was interrupted by the exception). This decision looks unlogical to me: every process stack has to have a…
Maxim
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What does the "Access" attribute mean in the bit [0] of the MEMATTRS signal from the CortexM4 IP and how do I assert the same

I wanted to know how to set the allocate bit (bit[0]) of the MEMATTRS signal (of the system bus) in the cortex m4 IP. What do I configure to get the bit to toggle? Also, I couldn't find any description in the cortex m4 manual talking about the…
cher
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MPU subregions security for STM32H7

I am trying to understand the STM32H7 MPU example, In this example, only one region has been created for all the memory address space 4GB. The subregion option is activated which means, it will be divided into 8 subregions starting from 0x0. And SRD…
Hamdim
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MPU settings for ARM Cortex M7

I am working on a SoC with several Cortex M7 cores. It has SRAM mapped to region 0x2000 0000 -> 0x3FFF FFFF and DDR mapped to 0x6000 0000 -> 0xDFFF FFFF. It seems that configuring the 4 partitions of DDR to cached normal memory (WT, WB or WBA) is…
calandoa
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