Extended page table for intel vmx address translation
Questions tagged [ept]
15 questions
3
votes
2 answers
In Intels extended page table (EPT), does the TLB cache guest virtual address to guest physical address?
I am reading about Intel's EPT to support virtualization. I read about the nested page table. My question is, does the TLB caches guest VA to guest PA as well as guest PA to host machine address? or is it just virtual address to machine address?

Keeto
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2
votes
1 answer
TLB Cache Invalidation when EPT Violation occurs?
I'm currently developing a hypervisor feature.
I'm confused about what to do with TLB Invalidation when EPT Violation occurs
I'm developing on Linux, using an i7 CPU. My implementation:
VPID and EPT Enabled
Initially, every EPT entries' write…

hayzjd836
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2
votes
1 answer
How do i know my CPU supports Docker?
What are now Docker cpu requirements for running in Linux, say, Ubuntu and Windows?
Is VT-x/AMD-v is enough or VT-d/AMD-Vi is required too?
Does it require MMU virtualization (Intel's Extended Page Tables (EPT) and Unrestricted Mode, and AMD's…

WebComer
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1
vote
0 answers
Nested KVM linux kernel bug in vmx.c
I am seeing the following kernel bug when EPT is enabled for a nested VM implementation.
Hoping you can guide me as to the root cause and remedy.
The background is I have a nested VM where the outer VM is based on an older version of Linux, from…

kevinmac
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1
vote
0 answers
Running nested virtualization with EPT over shadow paging with qemu-kvm
I'm experimenting with nested virtualization and using qemu-kvm.
I'm trying to run nested virtualization with shadow paging in the guest-host and EPT in the nested guest. Is there any way to do it?
I was able to run shadow paging in the nested guest…

CreamBrulee216
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1
vote
1 answer
How to determine instruction fetches are allowed or not by page table and EPT in x86-64?
Format of a Page-Table Entry that Maps a 4-KByte Page
Bit
Format of an EPT Page-Table Entry that Maps a 4-KByte Page
Bit
It seems EPT.bit2 and EPT.bit10 are used to determine whether instruction fetches are
allowed or not in Supervisor-mode \…

CNSpary
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1
vote
1 answer
How to set KVM VM use shadow page table?
I want to measure shadow page table performance vs EPT. I know in kvm code path, EPT and shadow page table share some code path. There is a switch to check if EPT is enabled.
So, I turn off EPT, I think this is a way to use shadow page table in KVM…

buweilv
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vote
3 answers
Intel EPT table is 4 level page table?
The figure is taken from here.
Q1. It seems that the EPT table keeps a whole copy of the guest page table, making it a 4-level page table. Is that correct?
Q2. Isn't it a bit of waste of space?
Q3. What exactly is an EPT violate? Does it mean…

Junji Zhi
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1
vote
1 answer
How to identify processors with Accessed and Dirty Flags for EPT
I want to find a Intel processor that support EPT accessed/dirty bits, but I can't find it till now. The Intel developer's manual just said that some processors support that, but it didn't make this clear.
I know that I can use rdmsr to determine if…

user3346981
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0
votes
0 answers
Locating VMCS in memory
I'm learning about Intel Virtualization stack and wondering if there is a possible way of spotting VMCS?
Let's say I'm running VMware Workstation on Windows or Linux and I have couple of VM's running. How can I spot VMCS for each running VM? I am…

Alex
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0
votes
0 answers
Any way to detect page swap from kernel or user mode
I want to build simple emulator using Intel VT-x.
Suppose we've allocated memory (guest RAM), of course from paged pool, and built EPT.
Everything working.
Now host OS (Win10 x64) decide to swap out those pages or move or smth else, so physical…

Vic3Dexe
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0
votes
0 answers
EPT violations through speculative execution
Can speculative execution cause an Extended Page Table (EPT) violation on x86 processors?
Assume I want to access a structure that has different Guest Physical Address (GPA) to Host Physical Address (HPA) mappings in two different EPTs. This…

CRoemheld
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0
votes
1 answer
Extended page table(ept)
Why can't we just get the GPA and then directly compute the real physical address, as shown in the https://www.exploit-db.com/docs/45546 on page 8? we can save a lot of access to memory.
Why do we need the complex calculation with nested page…

Moshe Levy
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0
votes
1 answer
Receiving data from Scanner via serial port
I want to receive data from a scanner through a serial port.
My scanner is connected to a EPT (Electronic Paiment Terminal) on COM0.
The scanner seems to work fine, I can detect barcodes and QrCodes but nothing is received on serial PORT.
Every…

DEMIR Cédric
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0
votes
1 answer
SLAT Can be avoided in HV?
This question might be funny (also i am very new to hypervisor).I have big confusion about SLAT (why it is required?).If i am not wrong SLAT(Second Level Address Translation) is used to do the address translation for guest virtual addr to actual…

Vignesh Waran
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