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I have a UVM testbench that uses configurations to replace a VHDL component that is deep within the design. Each test that I create has to use a verilog configuration to replace that component. Is there a way to use a variable for the hierarchical path so that I don't have to update each configuration if the VHDL design changes?

e19293001
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Pete
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2 Answers2

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There is no way to use a variable to represent a hierarchical path, except for virtual interface variables used to represent the hierarchical path to interface instances.

You will need to show use an example of how each test changes the VHDL component to give us a better idea for a solution; maybe you can use a macro.

dave_59
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  • Thanks, Dave. The test does not change the configuration of the VHDL component. Each test has a corresponding configuration, and if the design hierarchy changes, each configuration must be updated. I have all of the configurations in one file, so it is a simple find and replace, but I was hoping there was a more elegant solution, ideally only having to change the path name in one place. – Pete Jan 18 '16 at 17:08
  • If it is a simple search and replace then probably you can try some shell scripting to automate your tasks like [this](http://stackoverflow.com/questions/5171901/sed-command-find-and-replace-in-file-and-overwrite-file-doesnt-work-it-empties) and [this](http://unix.stackexchange.com/questions/159367/using-sed-to-find-and-replace) and [this](http://www.cyberciti.biz/faq/unix-linux-replace-string-words-in-many-files/) for example. – e19293001 Jan 19 '16 at 00:04
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I found a solution that does what I would like it to do. I have used macros to define the instances that I want to configure. The following is a an example of what I have done:

`define USE_TB_COMP instance top.u_mod1.u_sub_mod1.u_comp use tb_comp;

config test1_c;
    `USE_TB_COMP
endconfig
config test2_c;
    `USE_TB_COMP
endconfig
....
Pete
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