VHDL - Testbench internal signals

Question

I am spending some time learning about writing test benches to try out on some of the models I have produced. Does anyone know a way to monitor signals that are internal to the architecture of the unit under test. I have tried using

LIBRARY MODELSIM_LIB;
USE MODELSIM_LIB.UTIL.ALL;
    spy_process : process begin
        init_signal_spy("Q4/C1/A1/chip_sel","/chip_sel",1);
        wait;
        end process spy_process;

But I get a compiler error of the :

Error (10481): VHDL Use Clause error at Q4.vhd(15): design library "MODELSIM_lib" does not contain primary unit "util"

I've checked the Quartus II library folder and util is there in the correct place. Any suggestions? Thanks D

score 2 · Accepted Answer · edited May 23 '17 at 11:45

2

When you start a simulation, Quartus analyzes all files specified in the project settings (accessible via menu Assignment -> Settings -> Files). But, it elaborates only the entities which are required for the DUT starting from the top-level entity (see menu Assignment -> Settings -> General) to find out which design files (excluding testbenches) are required for simulation. For more details, see my other answer.

The library MODELSIM_LIB is found by ModelSim only, not by Quartus. Thus, Quartus-II fails to analyze your testbench file with the error posted in the question. But this is actually not required because it (should) only contain testbench code. Thus:

remove this testbench file from your Quartus project via menu Project -> "Add/Remove Files in Project...", and
add this file only in the simulation settings accessible via menu Assignment -> Settings -> Simulation -> Compile test bench -> Test Benches -> New/Edit.

edited May 23 '17 at 11:45

Community

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answered Feb 04 '16 at 08:15

Martin Zabel

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Not sure if I get you. I tried the steps you mentioned. made a separate file containing the test bench model. and removed it from the project. Then used it in the settings/simulation compile test bench section. Which worked fine. I get the option in modish to run the test bench. still no internal signals. If I add the code from the original question then the test bench is not usable when I run the simulation – hoboBob Feb 06 '16 at 10:46
@DannyJ I havn't used signal spy before. Thus. I checked only to load the `MODELSIM_LIB`. My solution fixes the error and thus answers the main part of the question. Could you make minimal and complete example to check for the `init_signal_spy`? – Martin Zabel Feb 07 '16 at 07:11

score 1 · Answer 2 · answered Feb 04 '16 at 10:03

Presumably you are using Modelsim to simulate, in which case you should not need anything more than to use the signal spy in VHDL, here is an example (excuse any syntax errors)...

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity my_testbench is

end my_testbench;

architecture behavioral of my_testbench is

    signal spy_blob : std_logic := '0';

begin

    my_entity : entity work.my_entity(rtl)
        port map(
            ...
            );

    spy_blob <= << signal .my_testbench.my_entity.w_blob : std_logic >>;

    my_monitor : process(w_clk)
    begin
        if(rising_edge(w_clk)) then
            if(spy_blob = '1') then
                -- do something
            end if;
        end if;
    end process;

end behavioral;

Note: this works with V13 of Quartus/Modelsim package.

Thanks for the reply. I tried this out but just get a compiler error with the syntax for spy_blob <= << signal .T1.rom.chip_sel : std_logic>> — hoboBob, Feb 06 '16 at 10:52

VHDL - Testbench internal signals

2 Answers2