Verilog code will simulate but won't synthesize.

Question

This is the code for my finite state machine

//
`timescale 1ns / 1ps
//Moore Finite State Machine Lab 3
// 
// WORKING, needs Screen output

module moore(
    input BTNC,    //manual clk
    input SW0,     //clr
    input SW1,    
    input SW2,     
    input SW3,    
    input SW4,
    output reg [3:0] LED,    //z
    reg [2:0] y,Y
    );
    localparam S_00=3'b000, S_01=3'b001, S_02=3'b010,
               S_03=3'b011, S_04=3'b100;

//Define next state
    always @(y,SW0,SW1,SW2,SW3,SW4)
    begin
            case (y)
                S_00: if (SW1)      Y <= S_01;
                      else          Y <= S_00;
                S_01: if (SW1)      Y <= S_02;
                      else if (SW3) Y <= S_03;
                      else          Y <= S_01;
                S_02: if (SW1)      Y <= S_04;
                      else          Y <= S_02;
                S_03: if (SW2)      Y <= S_04;
                      else if (SW3) Y <= S_02;
                      else          Y <= S_03;
                S_04: if (SW2)      Y <= S_02;
                      else if (SW4) Y <= S_00;
                      else          Y <= S_04;
                      default:      Y <= 3'bxxx;
            endcase
        end 

    //Define state update
    always @(SW0, BTNC)
       begin
        if (!SW0) y <= S_00;
        else y <= Y;
       end  

    //Define output
    always @(y)
        if (y==S_00)
            begin 
            assign LED = 3'b000;
            end
        else if (y==S_01)
            begin
            assign LED = 3'b001;
            end
        else if (y==S_02) 
            begin
            assign LED = 3'b010;
            end
        else if (y==S_03)
            begin 
            assign LED = 3'b011;
            end
        else if (y==S_04)
            begin 
            assign LED = 3'b100;
            end
        else
            begin 
            assign LED = 3'b000;  //not used
            end
endmodule // lab3ht codename moore

and when trying to synthesize in vivado 2015.3 this is what it tells me

[Common 17-69] Command failed: Vivado Synthesis failed
[Synth 8-285] failed synthesizing module 'moore' ["C:/Users/C/Desktop/moore3h/moore3/moore3.srcs/sources_1/new/moore.v":6]
[Synth 8-27] procedural assign not supported ["C:/Users/C/Desktop/moore3h/moore3/moore3.srcs/sources_1/new/moore.v":51]
[Synth 8-567] referenced signal 'Y' should be on the sensitivity list ["C:/Users/C/Desktop/moore3h/moore3/moore3.srcs/sources_1/new/moore.v":41]

I know that delays cannot be synthesized, and I tried fixing this by getting rid of always @(negedge BTNC) and using just the button press, but thats as far a my knowledge of verilog goes. I dont know why this cant be synthesized so i can later generate a bitstream and upload it to the basys3 board and use it there Any insight is greatly appreciated, The code runs beautifully during the simulation

score 4 · Accepted Answer · edited May 23 '17 at 12:09

Referring to the warnings. You have used assign statement in a procedural block making it a procedural continuous assignment.

[Synth 8-27] procedural assign not supported

These type of assignments are synthesizable by most of the tools, but they can easily be misused and hence avoided as far as possible. Your tool seems not supporting this type of statements. Hence, remove assign statement and use simple blocking statement in every if..else if..else condition.

// Remove assign
else if (y==S_04)
assign LED = 3'b100;
//...
// use simple blocking statements
else if (y==S_04)
LED = 3'b100;

Another warning related to Y is due to incomplete sensitivity list of always @(SW0, BTNC) block. You are using else y=Y; in this block. Henceforth Y must appear in sensitivity list.

[Synth 8-567] referenced signal 'Y' should be on the sensitivity list

For any combinational always block, the use of always@(*) or always_comb is recommended. This will remove any mistakes in providing manual sensitivity. You can convert the sensitivity of all the always blocks here (except for clocked always block) to always@(*).

Also, your next state logic always block is a combinational block. You must use blocking(=) assignments in that block.

always @(*)
    begin
            case (y)
                S_00: if (SW1)      Y = S_01; // blocking assignment
                      else          Y = S_00; // blocking assignment
//...

Refer to Procedural continuous assignment question for more information. Also, Verilog always block and Blocking vs Non-Blocking statments usage question links might be useful.

Verilog code will simulate but won't synthesize.

1 Answers1