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I am trying to implement the circuit mentioned at this question: How to perform right shifting binary multiplication?

I am getting the error:

Error (10170): Verilog HDL syntax error at mult.v(9) near text "="; expecting ".", or an identifier, or "["

I tried to Google it, but I couldn't find anything

Code:

module mult (multiplier, multiplicand, result, clk);

input [3:0] multiplier;
input [4:0] multiplicand;
input clk;
output [8:0] result;
reg [8:0] product;

initial
begin
    product [8:4] = 4'b00000;
    product [3:0] = multiplier [3:0];
end

assign result = product;

always @ (posedge clk)
begin
    if (product[0] == 1)
    begin
        product = product >> 1; // shift right, and assign the most significant bit to 0
        product[8:4] = product[7:3] + multiplicand[4:0]; // add 5-bits so we can handle the carry-out
    end
    else
    begin
        product = product >> 1; // shift to the right
    end
end

endmodule
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Ambitions
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1 Answers1

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The reason for your syntax error is that you cannot just write:

product [7:4] = 4'b0000;

you must write

assign product [7:4] = 4'b0000;

But, unless you are using System-Verilog (and your old-fashioned style of coding suggests you are not), you will find that 

assign product [7:4] = 4'b0000;

will not compile either, because the target of an assign statement must be a wire, not a reg. And if you change product to a wire, you will then find these statements give you and error:

product = product >> 1; // shift right, and assign the most significant bit to 0
product[7:3] = product[7:3] + multiplicand[4:0]; // add 5-bits so we can handle the carry-out

and

product = product >> 1; // shift to the right

because you cannot assign to a wire in an always (or initial) block.

You seem to be designing some kind of shift-and-add multiplier and presumably want to initialise product at the beginning of the calculation. (Assuming you sort the syntax) the lines 

(assign) product [7:4] = 4'b0000;
(assign) product [3:0] = multiplier [3:0];

drive product continuously, for all time; they do not initialise product. You are designing hardware here, not writing software.

Matthew Taylor
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  • I edited my question. How to solve this dilemma, if I fix the error with "wire", I will get another error, and it is the same for "reg." – Ambitions Dec 08 '16 at 13:26
  • There is no single correct answer, but I suspect `product` needs to be a `reg`. You will then have to execute some lines of code (in an `always` block) that initialise `product` at the right time. I didn't notice the first sentence in your question.The diagram you have linked to clearly shows a block called 'Control test'. You have not implemented this yet - but it is this that will control when `product` is initialised. The block 'Control test' is probably best implemented as an FSM. My point is: trying to initialise `product` with `assign` statements is completely wrong. – Matthew Taylor Dec 08 '16 at 14:00
  • I edited the code again, it has no errors, but the waveform is not showing the result. – Ambitions Dec 08 '16 at 15:25
  • @Ambitions Please don't keep editing the code in this question. The idea of this site is that questions become useful in future for people needing an answer to the same question. If you keep editing it, then that no longer becomes the case. Please ask a different question instead. – Matthew Taylor Dec 08 '16 at 15:41
  • @Ambitions I assume you will need to synthesise this. In which case, you cannot use an `initial` block; `initial` blocks are not synthesisable. As I said before, you need to remember you are designing hardware here, not writing software. (Perhaps forget Verilog for a while and) think how you would design such a circuit out of flip-flops and gates. You don't necessarily need to go right down to gate-level, but you certainly need a block diagram. (But you were given one of those in your original question.) So far, you have nothing that implements the 'Control test' block. As I said before... – Matthew Taylor Dec 08 '16 at 15:44
  • ...you probably need an FSM for that. I assume this is homework so, presumably you must have been taught about FSMs, because such a thing is probably necessary for this design. (If not an FSM, a counter could do it instead). The fact is, you need some hardware to control this, because this design has state; this design needs to cycle though various states as it performs the calculation. You need a part of the circuit (ideally an FSM) that stores that state in hardware (ie you need flip-flops to store that state). You cannot rely on _implicit state_ in hardware design. – Matthew Taylor Dec 08 '16 at 15:48
  • "_implicit state_"? _implicit state_ is where the state of the design depends on the actual line of code being executed. That's fine for software, but it's no good for hardware. All state of a hardware digital design must be stored in flip-flops. – Matthew Taylor Dec 08 '16 at 15:50