Instantiate vector of custom modules in Verilog with additional parameters

Question

I have a custom module in Verilog that takes several inputs and a few parameters.

module modA ( 
    input inp1, input inp2, ... output out);
    parameter my_addr;
...
endmodule

For various reasons associated with the specific hardware that I'm using, I need to create many instances of this module, each time with a different parameter (because my_addr corresponds to a specific location in memory that I am then accessing from the host). Moreover, I would like an easy way to access all of the outputs. I thought of doing something like

wire [9:0] outputs;
modA #(.my_addr) all_modA[9:0](.inp1(inp1), .inp2(inp2), .out(outputs));

So then I would have a vector of elements of all_modA, and the nth element of outputs would correspond to the nth instantiation of modA. That sounds like it would work well, except I need to pass a unique address to each instantiation. When I was just doing one instantiation at a time, it was quite easy to just define a parameter, but I don't see how I could pass a unique identifier each time.

Is there any way to accomplish this? The problem is, if I use a for loop, then I don't see how I can instantiate each modA with a unique identifier. If I don't use a for loop, then I'm not sure how to add a unique identifier.

score 2 · Answer 1 · edited May 23 '17 at 11:54

You can use a generate block over here. Generate blocks are evaluated during elaboration of the design. They do not execute at simulation time and the result is determined before the simulation begins. Therefore, all expressions in generate schemes shall be constant expressions, deterministic at elaboration time.

Give different values to my_addr according to the requirement. Also, you can apply some label identifier to begin-end block. This as an optional feature for generate blocks, but very highly recommended. By doing so, a unique hierarchical path can be seen to every instance of modA is different for each module.

For your code, I have created a testbench that instantiates the module with changing value of my_addr and outputs bus driving the out signal.

module modA #(parameter int my_addr) (input inp1, input inp2,output out);

  initial $display("%m: %d",my_addr);
endmodule

module top();
wire [9:0] outputs;
  genvar i; // generate iterator
  generate
    for(i=0;i<9;i++) begin: some_identifier
      // my_addr = i+1 for every module
      modA #(.my_addr(i+1)) all_modA(.inp1(inp1), .inp2(inp2), .out(outputs[i])); // Multiple modules
      end
  endgenerate
endmodule

For more information, refer to IEEE 1800-2012 Section 27. Similar questions can be found here and here.

It is **any** identifier of the `begin..end` block. This is a user-defined label of generate block. One can use any string over here. — sharvil111, May 04 '17 at 06:10
In my particular case, each output is a 16 bit wire. Would I then write "wire [15:0] outputs [0:10];"? — user147177, May 04 '17 at 18:08

Instantiate vector of custom modules in Verilog with additional parameters

1 Answers1