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i'm working on designing a mips processor using verilog in modelsim student version and we developed a c++ tool that converts assembly operations to machine code and save the result in .txt file so is there a way to make modelsim runs this tool when simulation starts ?

Mahmoud Megawer
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2 Answers2

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You can use $system("foo"); to run any system call from system verilog, including invoking your external C++ program, like ("echo hi"); or :

$system("path/to/my/cpp_binary.exe arg1 arg2 arg3");

If you wrap it in an initial block, you can run it at the beginning of simulation. See this answer.

Ross Rogers
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  • thanks that really helped ,but is there a way to reverse this process i mean can i compile a verilog file and simulate it from a another program without opening the modelsim gui ? – Mahmoud Megawer Dec 02 '17 at 22:28
  • modelsim has the concept of the "Command Line Interface" or CLI. If you want to compile your verilog and simulate it, you can create a Makefile to run all the compiler commands and invoke the simulation binary. Using a Makefile or shell script is how many chip companies do a lot of CLI interaction with the HDL tools. – Ross Rogers Dec 04 '17 at 00:53
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I think you meant you want to simulate an application running on your processor. To do that, you need to have a testbench that models memory with all the necessary connections to your processor. Then get your .txt file in a form that can be read by the $readmemh() system task. Then you load the contents of file into your memory.

dave_59
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