VHDL to Verilog

Question

I have some code in VHDL I am trying to convert to Verilog.

The VHDL code works fine

library ieee;                                
use ieee.std_logic_1164.all;                 
                                             
entity find_errors is port(                      
    a: bit_vector(0 to 3);                   
    b: out std_logic_vector(3 downto 0);         
    c: in bit_vector(5 downto 0));            
end find_errors;                            
                                             
architecture not_good of find_errors is        
  begin                                      
  my_label: process (a,c)                         
    begin                                    
    if c = "111111" then                                
      b <= To_StdLogicVector(a);                                
    else                                     
     b <= "0101";                            
    end if;                                   
  end process;                              
end not_good;

The Verilog code I have, gets errors "Illegal reference to net "bw"." and Register is illegal in left-hand side of continuous assignment

module find_errors(                            
  input  [3:0]a,                             
  output [3:0]b,                             
  input [5:0]c                               
);                                            
  wire [0:3]aw;                              
  wire [3:0]bw;                             
  reg [5:0]creg;                              
                                       
  assign aw = a;                             
  assign b = bw;                             
  assign creg = c;                          
always @(a,c)                                      
  begin                                      
    if (creg == 4'b1111)   
       bw <= aw;                              
    else                                     
     bw <= 4'b0101;                            
    end                                                          
endmodule

In order to be allowed to assign to `bw` in an `always` block, it needs to be declared as `reg`. On the other hand, `creg` must be declared as `wire`, not `reg`, in order to be allowed on the left-hand side of a continuous assignment (outside `always`). — mkrieger1, Jun 25 '20 at 17:49
Also note that `c` is 6 bits wide and you compare it with a 4-bit value. — mkrieger1, Jun 25 '20 at 18:01

score 0 · Answer 1 · answered Jun 25 '20 at 17:56

aw and creg are unnecessary, and bw needs to be declared as reg.

module find_errors(
  input  [3:0] a,
  output [3:0] b,
  input [5:0] c
);
                                                   
reg [3:0] bw;
assign b = bw;

always @(a,c)
begin
  if (c == 4'b1111)
    bw <= a;
  else
    bw <= 4'b0101;
end

endmodule

Since there is no sequential logic, you don't even need an always block:

module find_errors(
  input  [3:0] a,
  output [3:0] b,
  input [5:0] c
);
                                                   
assign b = (c == 4'b1111) ? a : 4'b0101;

endmodule

score 0 · Accepted Answer · answered Jun 25 '20 at 18:01

It looks pretty close but there are a few things that are problems/errors that need to be fixed, see inline comments in fixed code:

module find_errors(                            
  input  wire [3:0] a, // Better to be explicit about the types even if 
                       // its not strictly necessary                            
  output reg  [3:0] b, // As mentioned in the comments, the error youre
                       // seeing is because b is a net type by default; when 
                       // describing logic in any always block, you need to 
                       // use variable types, like reg or logic (for 
                       // SystemVerilog); see the comment for a thread 
                       // describing the difference     
  input wire [5:0] c);                             
  
  // You dont really need any local signals as the logic is pretty simple                       
  
  always @(*) begin // Always use either always @(*), assign or 
                    // always_comb (if using SystemVerilog) for combinational logic                                                                 
    if (c == 6'b111111)   
      b = a; // For combinational logic, use blocking assignment ("=") 
             // instead of non-blocking assignment ("<="), NBA is used for 
             // registers/sequential logic                              
    else                                     
      b = 4'b0101;                            
  end                                                          
endmodule

While a good rule of thumb, it's worth noting that this is not combinational logic *because* a blocking assignment is used. In this case, it doesn't make a difference. — mkrieger1, Jun 25 '20 at 18:04
For reference, the guideline is explained for example in section 11 in http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA.pdf — mkrieger1, Jun 25 '20 at 18:07

VHDL to Verilog

2 Answers2