RISCV32 vs RISCV64

Question

What are the differences between Riscv32 & Riscv64? I have been looking into the ISA docs, but cannot find it mentioned clearly anywhere, so pretty confused now.

I cannot find any docs about this from google, unfortunately. Any pointer?

Answer 1

RISC V has lots of options. RV32I and RV64I are base instruction sets, the 32-bit and 64-bit instruction sets, respectively.  There is also a 128 bit version, RV128I, and, a smaller 32-bit version RV32E, which has only 16 general purpose registers, whereas the others have 32 registers.  For all instruction sets, the base set are 32 bit instructions.

To the base instructions sets, they add optional extensions, e.g. for floating point, multiply and divide, etc.., so like RV32IMAC is based on RV32I with the M, A, and C extensions.

The main difference between RV32I, RV64I, and RV128I is the width of the registers, 32, 64, or 128 bits in width — along with an expected increase in address space from larger widths.  All instruction sets use 32-bit instructions, and with the compressed instruction option RVC, add 16-bit instructions to the mix.  No instructions of larger size are defined as standard yet, but there's opcode space for larger instruction, e.g. 48-bit, 64-bit and beyond that can be added to RV32 or RV64 (or RV128).

There are some opcode differences between RV32 and RV64 as well.  The larger widths add a few instructions to deal with the larger sizes.  RV64I, for example, uses the same opcode as RV32I for add, but means 64-bit add instead of 32-bit add, while there is a new opcode in RV64I for doing 32-bit only add (addw).  RV64I uses the same opcodes as RV32I for load and stores (for data of byte, half, and 32-bit word sizes), though includes new opcodes for loading/storing 64-bit data.

Otherwise one benefit of RV64 over RV32 is being able to address large address space than 4GB, which also applies to x86 vs. x64.  Since we can run out of space for data with a 32-bit address space, having a larger address space and being able to do 64-bit computations in 64-bit registers is the gist of why the processor is called a 64-bit processor (despite sharing the instruction size of 32 bits RV32) (this is also largely also true for x86 vs. x64, in that there is a large amount of similarity between them, such as variable length instructions ranging from 1 byte to 10 or so bytes.)

See also:

• https://content.riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf
• https://www.cnx-software.com/2019/08/27/risc-v-bases-and-extensions-explained/
• https://content.riscv.org/wp-content/uploads/2018/05/13.15-13-50-Talk-riscv-base-isa-20180507.pdf

Answer 2

The main difference between RISCV-64 and RISCV-32 is in the data-path, that the registers of the RISCV-64 CPU are 64 bits wide instead of being 32 bits wide as in RISCV-32 versions.

64-bit CPUs may or may not support 64-bit machine instructions, having uniform instruction length (lets say 32 bit instructions for both RISCV-64 & RISCV-32) is a plus point w.r.t branching and prediction of incoming machine instructions and hence CPU performance.