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Please explain the difference between two statement as they are behaving differently in side hardware.

reg [31:0]A;
wire B;
Statement 1
assign B = (A==32'h0)?(1'b1):(1'b0);
Statement 2
assign B = (A==32'h0);
Rsvay
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  • Are you getting different outputs ? Both statements should generate the same result. Statement 1 will be synthesized as a MUX + comparator and statement 2 is a comparator only. – Pradyuman Bissa Nov 08 '21 at 08:04
  • Please explain the difference in behaviors you are seeing. – dave_59 Nov 08 '21 at 18:46

1 Answers1

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I suspect the A contains 'x, this would make result in (A==32'h0) to be evaluated as 'x; then you have B = 1'bx.

What is the meaning of this in the circuit? I guess it 'x will be handled by the tool as Don't care and this will be used to further simplify the hardware.

#Edit: As noted by Serge in the comments, the ternary would give 'x not '0. A if('x) B=1'b1; else B=1'b0; in a procedural block would give '0, but not what the ternary does in verilog.

Bob
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  • not sure if you meant it correctly. Statement `1`, ternary operator, will return `x` if A is x. This is how such an operator works. Statement `2` will return `0` in such a case. – Serge Nov 08 '21 at 11:39
  • He is talking about hardware, not simulation. So why are you considering don't care? In my opinion he has some race conditions in his design and he get different synthesis result based on seed. – ToTamire Nov 08 '21 at 17:13
  • Thank you @Serge, for correcting me about the simulation result on the ternary. – Bob Nov 08 '21 at 18:48
  • @ToTamire, these guys talk about "don't care" in hardware https://stackoverflow.com/questions/29451175/. – Bob Nov 08 '21 at 18:48
  • There is a difference between a *don't care* and an *unknown value*. The example illustrates it. There is no don't care in hardware for this example, but there is a room for programming errors which can be checked by the first statement. Also, hardware *might* create a mux for the first statement and *might not* create one for the second. – Serge Nov 08 '21 at 19:57
  • I agree @Serge, a don't care is an input signal, an unknown is an output signal. If x is input to a logic that depends on it Synthesis will remove that logic, if the logic is not affected but it then it the synthesis will create a logic that doesn't depend on the input. The final circuit is only the logic that don't care about the 'x. I bet the we are far from what the author of the question expected now hehe, but is interesting discussion. Is good to learn how to adjust the communication with other members here :) – Bob Nov 08 '21 at 20:55
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    thanks @bob for you answer indeed this was the problem. – Rsvay Nov 15 '21 at 08:04