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I would like to check my work and understanding of pipelines, unfortunately MARS doesn't accommodate this feature so it is hard to verify my hypothesis.

I placed the instructions in a spreadsheet to help me understand what is going on and I would like to ensure that this is correct. I used the color blue to indicate each stage in the cycle, unlike the book, I didn't denote which half of the cycle each stage occurs (I.E WB is in the first half and ID in the second half)

Instruction pipeline

Based on the book by Patterson and Hennessey, the ID stage occurs towards the end while WB is at the start.

order of commands

So that should mean that the last SW command should work as intended because the WB of the prior (valid instruction) occurs at the start of that cycle - while ID is at the tail.

A P
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    Since you're showing a timing diagram with half-cycles for write/read of the register file: Fun fact: `IF` also happens [only in the 2nd half of a clock cycle](https://stackoverflow.com/a/58601958/224132) in classic MIPS (such as R2000), to keep branch latency down to 1 cycle by running branches in the 1st half-cycle of EX. That's why 1 branch delay slot can fully hide it. (Of course real-world classic MIPS *did* have bypass forwarding, but didn't need to know how to stall for anything except cache miss or mult/div: Microprocessor without Interlocked Pipeline Stages.) – Peter Cordes Apr 26 '22 at 23:14
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    A fake / simplified MIPS without branch-delay slots might also leave out that trick, and have a higher branch latency, so your diagram is presumably not wrong for the CPU they're considering. – Peter Cordes Apr 26 '22 at 23:15
  • @PeterCordes interesting! thanks... IF and ID happen no matter what for each instruction... I don't think there are many hazards in the IF stage (besides Branch and Jump). – A P Apr 27 '22 at 07:13
  • @PeterCordes my diagram is the top one, I randomly chose the color and didn't make any indication of when the write/read happens but rather a superficial view of the stages... the second diagram is from the Patterson/Hennessey book. – A P Apr 27 '22 at 07:14
  • Without bypass forwarding, WB -> ID is how you get data gets from previous instruction to later instructions, so it's the stage that matters in terms of whether there's a data hazard. If your pipeline detected hazards, that detection would happen there because that's where the pipeline looks at register numbers. And because register-fetch has to re-run in the 2nd half of the cycle when the critical WB runs (again, for the detect&stall instead of forward strategy). – Peter Cordes Apr 27 '22 at 07:25
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    Yes, IF is subject only to control hazards, e.g. when a load or store unexpectedly page-fault (or actually TLB-miss, since MIPS historically does software TLB management, with the OS having to provide a TLB miss-handler function). – Peter Cordes Apr 27 '22 at 07:27

1 Answers1

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Yes, that looks correct.

The ID stage of a succeeding instruction can overlap with the WB stage of a preceding instruction, and still get the proper value.

This is because, for one in WB, the new data is fully ready to go into the registers at the very start of the cycle — there is nothing to compute; the complete answers have been fully computed by the end of the prior cycle, so no bits need change in the values being recorded by the write back.  (Compare with ALU operation where substantial logic follows input from the prior cycle, before outputs can be computed.)

In the ID stage, the values are looked up in the register file, and either the cycle timing will be sufficiently long to allow the values to settle to include newly written WB values that happen in the same cycle, or else the designers will put an internal bypass/forward inside the register file.  Either way, the ID stage will obtain the latest value of a register that is written (WB) in the same cycle rather than a prior stale value.

The way they have put it is that WB happens in the first half of the cycle and ID happens in the second half.  However it is actually implemented internally to various processors — the idea is that we can count on reading values written in the same cycle.  (I believe they leave it unsaid as to whether they are suggesting to use the other transition of the clock (e.g. the downward edge) to physically divide the cycle in half or not, but that is another implementation possibility.)

From the same text book:

(A read of a register during a clock cycle returns the value written at the end of the first half of the cycle, when such a write occurs.)

Caption on Figure 4.52, and,

The last potential hazard can be resolved by the design of the register file hardware: What happens when a register is read and written in the same clock cycle? We assume that the write is in the first half of the clock cycle and the read is in the second half, so the read delivers what is written. As is the case for many implementations of register files, we have no data hazard in this case.

From main text just above the Figure 4.52.  These same texts occurs in the RISC V version of the book (though relative to Figure number 4.50 instead of 4.52).

Let's also note that when forwarding (aka bypassing) is introduced to mitigate hazards (instead of programmer inserting nops), there will need to be forwarding from EX->EX as well as MEM->EX.  The first is for back to back RAW hazards on the ALU, where the second is for both load-use RAW hazards (back to back) as well as ALU hazards that are separated by 1 instruction!

Erik Eidt
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  • Thank you! Yes, this exercise was meant to show us the different hazards and was a thought provoking one rather than anything practical... If we know where a NOP is needed, I think it helps gauge our understanding of the PIPELINE process and basic hazard detection. – A P Apr 27 '22 at 07:15