In this post, the question is seemingly addressed, but it leaves some room for questions about how this works in practice.
It is easy to understand why always @ (posedge clk) makes logic from flip flops (because flip flops are updated every clock cycle), but why differentiate with a different "always" construct?
Is there any chance that always @ (posedge clk) won't create logic from flip flops somehow? Is this more important in digital design for ASICs than in FPGAs?
If always_ff = always @ (posedge clk)
That is an incorrect assumption.
Just like with always, always_ff can have different sensitivity lists. Here are a few examples:
always_ff @(posedge clk)
always_ff @(negedge spi_clock)
always_ff @(posedge reset or negedge nClk)
Any signal name can be used for the clock signal, an asynchronous reset signal can also be optionally specified, and any combination of polarities can be used.
Both always and always_ff keywords can be used to model sequential logic (such as flip-flops). Both can infer flip-flops for synthesis of ASICs or FPGAs.
always_ff was introduced into the language to offer different semantics. It conveys more specific design intent than the general always (which can also be used to infer combinational logic).
Refer to IEEE Std 1800-2017, section 9.2.2.4 Sequential logic always_ff procedure.
Another advantage:
Software tools should perform additional checks to warn if the behavior within an
always_ffprocedure does not represent sequential logic.
