Questions tagged [zero-extension]
28 questions
172
votes
4 answers
Why do x86-64 instructions on 32-bit registers zero the upper part of the full 64-bit register?
In the x86-64 Tour of Intel Manuals, I read
Perhaps the most surprising fact is that an instruction such as MOV EAX, EBX automatically zeroes upper 32 bits of RAX register.
The Intel documentation (3.4.1.1 General-Purpose Registers in 64-Bit Mode…
Nubok
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93
votes
1 answer
x86_64 registers rax/eax/ax/al overwriting full register contents
As it is widely advertised, modern x86_64 processors have 64-bit registers that can be used in backward-compatible fashion as 32-bit registers, 16-bit registers and even 8-bit registers, for example:
0x1122334455667788
================ rax (64…
GreyCat
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49
votes
2 answers
What does the MOVZBL instruction do in IA-32 AT&T syntax?
What exactly does this instruction do?
movzbl 0x01(%eax,%ecx), %eax
user663896
15
votes
1 answer
Clarifications on signed/unsigned load and store instructions (MIPS)
I can't seem to grasp the concept on these stuff, even with the help of Google and a textbook in my hand.
Following the format (opcode, rs, rt, offset)...
Do you sign extend the offset before adding it to the value of the address? Or add before…
Check
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7
votes
1 answer
Can "mov eax, 0x1" always be used instead of "mov rax, 0x1"?
When assembling this code with nasm:
BITS 64
mov eax, 0x1
mov rax, 0x1
I get this output:
b8 01 00 00 00 b8 01 00 00 00
which is the opcode for mov eax, 0x1 repeated twice.
Does this mean that mov rax, 0x1 can always be replaced by mov eax, 0x1 or…
Tyilo
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5
votes
1 answer
Weird results with movzwl, %ax and negative values
Alright, so I am dealing with the following snippet of code:
push %ebp
mov %esp,%ebp
push %ebx
mov 0x8(%ebp),%eax
movzwl %ax,%edx
So this behaves as expected when dealing with positive values. The value copied into %edx is the…
ebensing
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5
votes
1 answer
Why movzbl is used in assembly when casting unsigned char to signed data types?
I'm learning data movement(MOV) in assembly.
I tried to compile some code to see the assembly in a x86_64 Ubuntu 18.04 machine:
typedef unsigned char src_t;
typedef xxx dst_t;
dst_t cast(src_t *sp, dst_t *dp) {
*dp = (dst_t)*sp;
return…
Sean
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5
votes
4 answers
MASM Assembly move 8 bit register to the 16 bit register (ie. mov cx, ch)
I decided to learn an assembly programming language. I am using this 8086 tutorial. At the bottom the exercise is to find an error in some instructions and one of them is
mov cx, ch
I found some similar question on SO on this topic explaining how…
Bartłomiej Szałach
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5
votes
2 answers
In MIPS, when to use a signed-extend, when to use a zero-extend?
I am designing a MIPS processor as my individual project, by now I met a very confused question. I just can not summarize when to use signed-extend and when to use zero-extend in MIPS.
I have searched lots of resources, mostly said:
1) ADDI, ADDIU…
Shuaiyu Jiang
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4
votes
1 answer
What do the `uxtx` and `sxtx` extensions mean for 32-bit AArch64 `adds` instruction?
I'm looking at the following disassembled AArch64 instruction:
65 6E 20 2B adds w5, w19, w0, uxtx #3
According to the ARM manual, uxtx zero-extends w0 to an unsigned 64-bit value before adding it to the value in w19. But w19 is a 32-bit "slice"…
John Källén
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3
votes
1 answer
Adding a byte from memory to the AX register
I'm currently trying to figure out how to add the first byte in memory pointed to by the pointer register SI to the current contents of the AX register.
So if SI holds some address, and the values in memory at that address are: 00 and 01, I'm…
CompSciStudent
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2
votes
3 answers
Zero/sign-extend are no-op, why then instructions for each size type?
For x86 and x64 compilers generate similar zero/sign extend MOVSX and MOVZX. The expansion itself is not free, but allows processors to perform out-of-order magic speed up.
But on RISC-V:
Consequently, conversion between unsigned and signed 32-bit…
yudre
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- 2
2
votes
3 answers
andi vs. addi instruction in MIPS with negative immediate constant
Assume $t2=0x55555550, then executing the following instruction:
andi $t2, $t2, -1
$t2 becomes 0x0005550
This is confirmed by the MIPS emulator1
However, it is not what I expected. I think the answer should be 0x55555550 & 0xFFFFFFFF =…
Lin Yu Cheng
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1
vote
1 answer
Assembly (AT&T) read memory to register?
In assembly I am trying to add 32 bits from memory to 64 registers, this will load 64 bits:
add arr(,%rax,4), %rbx
So I tried:
add arr(,%rax,4), %rbx
which didn't work.
How can I solve this?
user15563851
1
vote
0 answers
Didn't understand the movzx command
I didn't understand what this command does, for example:
'movzx eax, byte [rax]'
Before the command executed the value of rax was : '0x7ffff253c523' and after this line it became '0x00000070', why?
I can really use some explanation or example,…
roye1233
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