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I faced a problem when using Quartus II from Altera. In the VHDL course, I have a problem about the behavior of VHDL variables VS signals. The theory says that the VHDL variables get its new value immediately. On the other hand , the signal's new value requires a delay. So the result is different between the two cases. But this is not what happens when I use Quartus tool. I unexpectedly get the same result for both. I don't Know why this happens, please advise??

Heba
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    Show us what you were working on. – Qiu Apr 09 '15 at 17:41
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    The process will run and update both the variable and the signal within the same clock, the simulator will probably show that they both update on the same clock edge. However, within the process, the signal will not update immediately, but the variable will. To better understand this, check this out: http://stackoverflow.com/questions/15485749/vhdl-variable-vs-signal . Let me know If you are still confused after reading that link and I can post an actual answer on this thread to more specifically address your issue! – NKamrath Apr 09 '15 at 17:53

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If your assignments all go without an explicit delay clause like 

y <= x after 10 ns;
then the difference is a single delta cycle. A delta cycle is no physical time and is not visible in the waveform. You will see a difference though when you use either the updated variable or signal to assign to another output signal later in the same process. Assigning from the variable copies its newly computed value, assigning from the signal copies the value it started with into the current delta cycle.
Thomas B Preusser
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You should get the same result. There shouldn't be any delay. In programs which use VHDL, the programs operate so fast that you can't measure a delay. If you want a delay you can use the "wait for x ns" command.

user6210457
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