I'm very new to VHDL and for my digital design project I have to make a simulation of a washing machine in a DE10-Lite FPGA with finite states.
Everything seems good so far but when it's turn for the impure function Wash to work, it looks like signal sec is not summing up one, and therefore never leaves the state.
Any idea on how to correct this?
This is the full code. Impure Wash function is declared in the second process and signal sec is part of the architecture variables.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
entity WM is --Wash
port (
p,m,s,w,r,d,c,t: in std_logic; --power,mode,start,wash,rinse,dry,clock,tank
pl,ml,wl,rl,dl,motor: out std_logic --powerLed,modeLed,washLed,rinseLed,dryLed,motor
);
end WM;
architecture bhv of WM is
signal sec: integer:= 0;
signal e: boolean := false;
type t_state is (off,autoL,autoP,manualL);
signal state : t_state;
begin
process(p,m,w,r,d,s)
begin
if p = '0' then
state <= off; --off
else
if m = '1' then
state <= autoL; --auto
if s = '1' then
state <= autoP;
else
state <= autoL;
end if;
else
state <= manualL; --manual
end if;
end if;
end process;
process(state,c,t,e,sec)
impure function WashFill(Seconds : integer:= 0) return boolean is
begin
if t = '1' then
return true;
else
if c = '1' then
wl <= '0';
else
wl <= '1';
end if;
return false;
end if;
end function;
impure function Wash(Seconds : integer:= 0) return boolean is
begin
if c = '1' then
sec <= sec + 1;
else
sec <= sec;
end if;
if sec = 5 then
sec <= 0;
motor <= '0';
return true;
else
motor <= '1';
wl <= '1';
return false;
end if;
end function;
impure function WashDrain(Seconds : integer:= 0) return boolean is
begin
if t = '0' then
return true;
else
if c = '1' then
wl <= '0';
else
wl <= '1';
end if;
return false;
end if;
end function;
begin
case state is
when off =>
pl <= '0';
ml <= '0';
wl <= '0';
rl <= '0';
dl <= '0';
motor <= '0';
when autoL =>
pl <= '1';
ml <= '1';
wl <= '1';
rl <= '1';
dl <= '1';
motor <= '0';
when autoP =>
if WashFill(Seconds => 5) then
if Wash(Seconds => 5) then
if WashDrain(Seconds => 5) then
end if;
end if;
end if;
when manualL =>
pl <= '1';
ml <= '0';
wl <= '0';
rl <= '0';
dl <= '0';
motor <= '0';
--when others =>
--motor <='1';
end case;
end process;
end bhv;
