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I am having a problem with the following code which should simply throw an error at compilation if my number of inputs is not divisible by my number of outputs.

module multiplexer #(parameter N_INPUTS, parameter N_OUTPUTS) (in, out, select);

    generate
        if (N_INPUTS % N_OUTPUTS != 0) begin
            $error("%m ** Illegal Parameter ** NUMBER OF INPUTS(%d) does not divide into NUMBER OF OUTPUTS(%d)", N_INPUTS, N_OUTPUTS);
        end
    endgenerate

    input wire [N_INPUTS-1:0] in;
    input wire [$clog2(N_INPUTS/N_OUTPUTS) - 1:0] select;
    output wire [N_OUTPUTS-1:0] out;

    always @ (select, in) begin
        out = in[(select + 1) * N_OUTPUTS - 1:(select + 1) * N_OUTPUTS - N_OUTPUTS];
    end

endmodule

But Quartus keep throwing me this error when I proceed to an Analysis:

Error (10170): Verilog HDL syntax error at multiplexer.v(5) near text: "$error";  expecting "end". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

I am beginning to wonder wether or not the compiler of Quartus supports the $error command (it's my first time using it).

I would greatly appreciate any help on the subject since I am still a beginner in the domain :)

toolic
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Zacharie McCormick
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  • I'll try that. Just let me a couple of minutes to know how to enable this thing :P – Zacharie McCormick Apr 23 '20 at 15:39
  • Does SystemVerilog have the same syntax and everything (just more feature basically)? Because when I look online it tells me to change the extension of my file from .v (for Verilog) to .sv (for SystemVerilog). – Zacharie McCormick Apr 23 '20 at 15:44
  • I'll try finding a way to simply activate it because if I change my file to SystemVerilog I think my other file may start bleeding errors as they all contain always block and I am noticing that SystemVerilog as some special always block for every type of logic. But thank you for all the help I am pretty sure that this question is now solved. I would have liked to mark your answer as the right one but you only commented... – Zacharie McCormick Apr 23 '20 at 15:50

3 Answers3

3

Close your Quartus project and in the .qsf file, change the line pointing to your multiplexer module verilog file from:

set_global_assignment -name VERILOG_FILE multiplexer.v

To:

set_global_assignment -name SYSTEMVERILOG_FILE multiplexer.v

Edit:

Also set: 

set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2009

Edit 2:

It's a SystemVerilog 2009 feature and Quartus Prime Standard and Quartus Prime Lite don't support VHDL 2008 or SystemVerilog 2009.

Quartus Prime Pro 19.4:

enter image description here

Quartus Prime Standard 19.1:

enter image description here

Charles Clayton
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  • Yeah I tried excluding every file from project then changing their extension to .sv and reimporting them in the project (which had the same effect as your little trick but it required also changing the extension). Alas it is not working. I also told Quartus to compile my Verilog HDL as SystemVerilog but without success... At this point I don't even understand what is going wrong in this file... – Zacharie McCormick Apr 23 '20 at 16:13
  • Altough in my .qsf it mention this line : set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005. Could the version be wrong? Haven't found a way to change it in Quartus itself. – Zacharie McCormick Apr 23 '20 at 16:16
  • If you can't find a place to change these values in the GUI itself, you can change the [settings](https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl-pro-qsf-reference.pdf) in the `.qsf` directly. You can try changing the version to `SystemVerilog_2009` but I don't know if you'll see much difference. Is the error you see still the same as in the body? – Charles Clayton Apr 23 '20 at 16:23
  • Yes it's still the same error. I also recreated the project and imported my file which have .sv extensions now and I still get the same error. I'll go ahead and try 2009. EDIT: Quartus simply deletes the change and retries compilation with the old 2005 parameter. – Zacharie McCormick Apr 23 '20 at 16:28
  • I see this warning `Warning(17326): Verilog HDL warning at multiplexer.sv(5): elaboration system task error violates IEEE 1800 (2005) syntax`, so perhaps the SystemVerilog 2009 *will* help. – Charles Clayton Apr 23 '20 at 16:37
  • Could you tell me what you did to get this warning? Because I don't have it and as I mentionned, modifying the .qsf file only makes Quartus reset the file. – Zacharie McCormick Apr 23 '20 at 16:41
  • I threw your code (with the fixes mentioned by Matthew Taylor) into a Quartus Prime Pro 19.4 project and ran "Analysis & Synthesis" with default settings. If I change to 2009 using the command above, I don't see the warning. What version of Quartus are you using? Also, you need to close Quartus before modifying the QSF, otherwise yes the active project will reset it. – Charles Clayton Apr 23 '20 at 16:47
  • I tried changing the 2005 to 2009 while Quartus was closed but now when I open my project I get this `125036 Assignment value SYSTEMVERILOG_2009 for assignment VERILOG_INPUT_VERSION is illegal` – Zacharie McCormick Apr 23 '20 at 16:48
  • I should also mention that I am using the lite version of Quartus Prime. When I look online I should be able to select SysteVerilog 2009 in the settings but I only have SystemVerilog as an option... PLease don't tell me you need to pay to get this feature... – Zacharie McCormick Apr 23 '20 at 16:54
  • I have Quartus Prime Lite 19.1 which i download a week ago... I'll go look into why I don't have the 19.4. EDIT: Yeah there is no version higher than 19.1 for the Lite version. You have the Pro version (I don't have the money for that because I'm a student) – Zacharie McCormick Apr 23 '20 at 17:07
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    I tested it in both standard and prime and yeah, that's the problem. Quartus Prime Standard and Quartus Prime Lite don't support VHDL 2008 or SystemVerilog 2009. – Charles Clayton Apr 23 '20 at 17:22
  • I'll accept you answer because it resolves the initial problem which was related to Quartus Prime in general and my problem now is more about the version I am using. – Zacharie McCormick Apr 23 '20 at 17:22
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I found the problem...money... If you look at the following image you'll notice that if you are poor you can't use the latest version of SystemVerilog in the Lite and Standard version of Quartus Prime. enter image description here

Well that explains it all. If anyone as another solution to throw error at compile time that looks better than this please tell me:

generate
if (CONDITION > MAX_ALLOWED /* your condition check */ ) begin
    illegal_parameter_condition_triggered_will_instantiate_an non_existing_module();
end
endgenerate

Note: this was taken from https://electronics.stackexchange.com/a/71226

Zacharie McCormick
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I see other errors:

  • you are driving wire out from a procedural block (your always block). You cannot do that, you can only drive a variable. ie out must be a variable.

  • your code inside the square brackets is illegal. You will need to use one of the +: or -: operators. See this answer here.

Matthew Taylor
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  • Although the question seems to be about Verilog, note that $error etc are legal outside of procedural blocks, usually for the very purpose of generate block DRC, in SystemVerilog (elaboration system tasks.) – gatecat Apr 23 '20 at 08:38
  • Thank you for the advice on this new operator. It is so much easier than having to think about it with those variables XD – Zacharie McCormick Apr 23 '20 at 15:39